1.Blocks design and integration 2.Block level simulation and verification 3.Chip level simulation and verification for own blocks 4.Run all digital design flow(synthesis/STA/lint/LEC/...) What we expect to see: 1.BS, MS or PhD in electrical engineering, computer engineering or computer science with a special focus on digital system design, computer architecture or computer hardware design. 2.8-15 years of industry experience 3.Experience in RTL design(design many modules from scratch). 4.Good at Verilog and SystemVerilog What we would be happy to see: 1.Experience in bus interface design, SoC integration 2.Experience in standard interfaces protocols(USB/PCIe/...) and common IP blocks. 3.Experience in design flows such as synthesis, design for testing(DFT), static timing analysis(STA), logic equivalence check(LEC), CDC,... etc. 4.Experience in chip tape-out and volume production, especially in sub-40nm nodes. 5.Skilled in system verification such as FPGA prototype buildup and debug. 6.Familiarity with script programming such as shell script, make, Python, etc. 7.Willing to take on challenges, team player 8.Effective English communications for cross site co-work